AD9211_17 datasheet(4/29 Pages) AD

部品番号	AD9211

部品情報	1.8 V Analog-to-Digital Converter

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AD9211

Rev. 0 | Page 3 of 28

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 1.

AD9211-200

AD9211-250

AD9211-300

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

10

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

25°C

4.3

4.6

4.4

mV

Full

−12

+12

−13

+13

−13

+13

mV

Gain Error

25°C

1.0

1.3

1.1

% FS

Full

−2.2

+4.3

−2.2

+4.3

−2.2

+4.3

% FS

Differential Nonlinearity (DNL)

25°C

±0.1

LSB

Full

−0.5

+0.5

−0.5

+0.5

−0.5

+0.5

LSB

Integral Nonlinearity (INL)

25°C

±0.2

LSB

Full

−0.35

0.35

−0.45

0.45

−0.7

+0.7

LSB

TEMPERATURE DRIFT

Offset Error

Full

±8

±7

±6

μV/°C

Gain Error

Full

0.018

%/°C

ANALOG INPUTS (VIN+, VIN−)

Differential Input Voltage Range2

Full

0.98

1.25

1.5

0.98

1.25

1.5

0.98

1.25

1.5

V p-p

Input Common-Mode Voltage

Full

1.4

V

Input Resistance (Differential)

Full

4.3

kΩ

Input Capacitance

25°C

2

pF

POWER SUPPLY

AVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Full

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

Supply Currents

IAVDD3

Full

134

144

158

169

189

203

mA

IDRVDD3/SDR Mode4

Full

51

54

53

55

54

57

mA

IDRVDD3/DDR Mode5

Full

35

38

39

mA

Power Dissipation3

Full

mW

SDR Mode4

Full

333

356

380

403

437

468

mW

DDR Mode5

Full

304

353

410

mW

1 See the AN-835

application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.

3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.

4 Single data rate mode; this is the default mode of the AD9211.

5 Double data rate mode; user-programmable feature. See the Memory Map section.

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