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AD9252ABCPZRL7-50 データシート(PDF) 7 Page - Analog Devices

部品番号 AD9252ABCPZRL7-50
部品情報  Serial LVDS, 1.8 V ADC
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9252ABCPZRL7-50 データシート(HTML) 7 Page - Analog Devices

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AD9252
Data Sheet
Rev. E | Page 6 of 52
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9252-50
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK2
Maximum Clock Rate
Full
50
MSPS
Minimum Clock Rate
Full
10
MSPS
Clock Pulse Width High (tEH)
Full
10.0
ns
Clock Pulse Width Low (tEL)
Full
10.0
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
1.5
2.3
3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
1.5
2.3
3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/28)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/28) − 300
(tSAMPLE/28)
(tSAMPLE/28) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/28) − 300
(tSAMPLE/28)
(tSAMPLE/28) + 300
ps
Data-to-Data Skew (tDATA-MAX − tDATA-MIN)
Full
±50
±200
ps
Wake-Up Time (Standby)
25°C
600
ns
Wake-Up Time (Power-Down)
25°C
375
μs
Pipeline Latency
Full
8
CLK cycles
APERTURE
Aperture Delay (tA)
25°C
750
ps
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
Out-of-Range Recovery Time
25°C
1
CLK cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI.
3
Measurements were made using a part soldered to FR-4 material.
4
tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.


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