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AD9267EBZ データシート(PDF) 9 Page - Analog Devices |
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AD9267EBZ データシート(HTML) 9 Page - Analog Devices |
9 / 25 page AD9267 Rev. 0 | Page 8 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK– CVDD PDWNA PDWNB PLL_LOCKED DVDD DGND DRVDD D0–B D0+B D1–B D1+B D2–B D2+B D3–B D3+B SCLK/PLLMULT0 SDIO/PLLMULT1 PLLMULT2 PLLMULT3 PLLMULT4 DVDD DGND DRVDD D3+A D3–A D2+A D2–A D1+A D1–A D0+A D0–A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9267 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Differential Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3, 4 PDWNA, PDWNB Power-Down Pins. Active high. 5 PLL_LOCKED PLL Lock Indicator. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply 9 to 16 D0−B, D0+B to D3−B, D3+B Channel B Differential LVDS Data Output Bits. D0+B is the LSB and D3+B is the MSB. 17, 18 OR−B, OR+B Channel B Overrange Indicator Pins. 19, 20 DCO−, DCO+ Differential Data Clock Output. 21, 22, 26 to 30 DNC Do Not Connect. 31, 32 OR−A, OR+A Channel A Overrange Indicator Pins. 33 to 40 D0−A, D0+A to D3−A, D3+A Channel A Differential LVDS Data Output Bits. D0+A is the LSB and D3+A is the MSB. 44, 45, 46 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 47 SDIO/PLLMULT1 Serial Port Interface Data Input/Output/PLL Mode Selection Pins. 48 SCLK/PLLMULT0 Serial Port Interface Clock/PLL Mode Selection Pins. 49 CSB Serial Port Interface Chip Select Pin Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53, 54 VIN+A, VIN−A Channel A Analog Input. 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59, 60 VIN+B, VIN−B Channel B Analog Input. 63 CGND Clock Ground. 64 CLK+ Differential Clock Input (+). 65 Exposed paddle (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed paddle must be soldered to analog ground of the PCB to achieve optimal electrical and thermal performance. |
同様の部品番号 - AD9267EBZ |
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同様の説明 - AD9267EBZ |
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