AD9237 datasheet(10/25 Pages) AD

部品番号	AD9237

部品情報	3 V Low Power A/D Converter

Download	25 Pages

Scroll/Zoom	100%

メーカー	AD [Analog Devices]

ホームページ	http://www.analog.com

Logo

10 / 25 page

Data Sheet

AD9237

Rev. C | Page 9 of 24

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay (tA)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Aperture Jitter (tJ)

The sample-to-sample variation in aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code from a line drawn from

negative full scale through positive full scale. The point used

as negative full scale occurs ½ LSB before the first code

transition. Positive full scale is defined as a level 1½ LSBs

beyond the last code transition. The deviation is measured

from the middle of each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 12-bit resolution indicates that all 4096

codes must be present over all operating ranges.

Offset Error

The major carry transition should occur for an analog value

½ LSB below VIN+ = VIN–. Offset error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value

½ LSB above negative full scale. The last transition should occur

at an analog value 1½ LSB below the positive full scale. Gain

error is the deviation of the actual difference between first and

last code transitions and the ideal difference between first and

last code transitions.

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

at TMIN or TMAX.

Power Supply Rejection Ratio

The change in full scale from the value with the supply at the

minimum limit to the value with the supply at its maximum

limit.

Total Harmonic Distortion (THD)1

The ratio of the rms sum of the first six harmonic components

to the rms value of the measured input signal.

Signal-To-Noise and Distortion (SINAD)1

The ratio of the rms signal amplitude to the rms value of the

sum of all other spectral components below the Nyquist

frequency, including harmonics but excluding dc.

Effective Number of Bits (ENOB)

The effective number of bits for a device for sine wave inputs

at a given input frequency can be calculated directly from its

measured SINAD using the following formula:

ENOB = (SINADdBFS − 1.76)/6.02

Signal-to-Noise Ratio (SNR)1

The ratio of the rms signal to the rms value of the sum of all

other spectral components below the Nyquist frequency,

excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)1

SFDR is the difference in dB between the rms amplitude of the

input signal and the rms value of the peak spurious signal. The

peak spurious signal may not be an harmonic.

Two-Tone SFDR1

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the clock

pulse should be left in the Logic 1 state to achieve rated

performance. Pulse width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed

limit.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Output Propagation Delay (tPD)

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

Out-of-Range Recovery Time

The time it takes the ADC to reacquire the analog input after a

transition from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to 10%

below positive full scale.

1

AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

同様の部品番号 - AD9237

メーカー	部品番号	データシート	部品情報
Analog Devices	AD9237	1,005Kb / 28P	12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter REV. 0
	AD9237BCP-20EB	1,005Kb / 28P	12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter REV. 0
	AD9237BCP-20EB	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0
	AD9237BCP-40EB	1,005Kb / 28P	12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter REV. 0
	AD9237BCP-40EB	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0

More results

同様の説明 - AD9237

メーカー	部品番号	データシート	部品情報
Analog Devices	AD9229	785Kb / 41P	Serial, LVDS, 3 V A/D Converter
Analog Devices	AD9289	917Kb / 33P	Serial LVDS 3 V A/D Converter
Maxim Integrated Produc...	MAX136	172Kb / 4P	Low Power, 3?밆igit A/D Converter With Display Hold
Analog Devices	AD9237	1,005Kb / 28P	12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter REV. 0
Analog Microelectronics	AME7106	1Mb / 20P	3-1/2 Digit A/D Converter High Accuracy, Low Power
Intersil Corporation	ICL7126	468Kb / 15P	3 1/2 Digit, Low Power, Single Chip A/D Converter
Analog Devices	AD9237	570Kb / 24P	12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter REV. C
Renesas Technology Corp	ICL7126	790Kb / 15P	3 1/2 Digit, Low Power, Single Chip A/D Converter
National Semiconductor ...	ADC083000	1Mb / 40P	8-Bit, 3 GSPS, High Performance, Low Power A/D Converter
Cyrustek corporation	ES5136	692Kb / 22P	3 1/2 DIGIT A/D CONVERTER W/LCD(Low power)