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AD9236BCPZRL7-80 データシート(PDF) 1 Page - Analog Devices |
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AD9236BCPZRL7-80 データシート(HTML) 1 Page - Analog Devices |
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1 / 37 page  12-Bit, 80 MSPS, 3 V A/D Converter Data Sheet AD9236 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70.4 dBc to Nyquist SFDR = 87.8 dBc to Nyquist Low power: 366 mW Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer APPLICATIONS High end medical imaging equipment IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes DTV subsystems GENERAL DESCRIPTION The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS analog-to-digital converter featuring a high performance sample- and-hold amplifier (SHA) and voltage reference. The AD9236 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9236 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is FUNCTIONAL BLOCK DIAGRAM 03066-0-001 DRVDD AVDD AGND 0.5V CLK PDWN MODE DGND OTR VIN+ VIN– REFT REFB AD9236 VREF SENSE SHA A/D MDAC1 4 16 12 3 A/D 8-STAGE 1 1/2-BIT PIPELINE REF SELECT CLOCK DUTY CYCLE STABILIZER MODE SELECT CORRECTION LOGIC OUTPUT BUFFERS D11 (MSB) D0 (LSB) Figure 1. presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. The AD9236 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW. 3. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz, and can be configured for single-ended or differential operation. 4. The AD9236 is pin compatible with the AD9215, AD9235, and AD9245. This allows a simplified migration from 10 bits to 14 bits and 20 MSPS to 80 MSPS. 5. The DCS maintains overall ADC performance over a wide range of clock pulse widths. 6. The OTR output bit indicates when the signal is beyond the selected input range. |
同様の部品番号 - AD9236BCPZRL7-80 |
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同様の説明 - AD9236BCPZRL7-80 |
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