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OPT8241NBNL データシート(PDF) 8 Page - Texas Instruments |
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OPT8241NBNL データシート(HTML) 8 Page - Texas Instruments |
8 / 34 page OPT8241 SBAS704B – JUNE 2015 – REVISED OCTOBER 2015 www.ti.com Electrical Characteristics (continued) All specifications at TA = 25°C, VAVDDH = 3.3 V, VAVDD = 1.8 V, VVMIXH = 1.5 V, VDVDD = 1.8 V, VDVDDH = 3.3 V, VPVDD = 3.3 V, VSUB_BIAS = 0 V, integration duty cycle = 10%, system clock frequency = 48 MHz, modulation frequency = 50 MHz, and 850 nm illumination, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS I/Os VIH Input high-level threshold 0.7 × VCC(1) V VIL Input low-level threshold 0.3 × VCC(1) V IOH = –2 mA VCC(1) – 0.45 VOH Output high level V IOH = –8 mA VCC(1) – 0.5 IOL = 2 mA 0.35 VOL Output Low Level V IOL = 8 mA 0.65 Pins with pullup, pulldown resistor ±50 II Input pin leakage current µA Pins without pullup, pulldown ±10 resistor CI Input capacitance 5 pF IOH 10 Output current mA IOL 10 (1) VCC is equal to IOVDD or DVDDH, based on the I/O bank listed in the Pin Functions table. 6.6 Timing Requirements MIN NOM MAX UNIT MCLK duty cycle 48% 52% MCLK frequency 12 50 MHz VD_IN pulse duration 2 × MCLK period ns RTSZ low pulse duration (reset) 100 ns 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted); VDVDD = 1.8 V, VDVDDH = 3.3 V, and VIOVDD = 1.8 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DDR LVDS MODE tSU Data setup time Data valid to zero crossing of DCLKP, DCLKM 0.48 ns tH Data hold time Zero crossing of DCLKP, DCLKM to data becoming invalid 0.54 ns tFALL, tRISE Data fall time, data rise time Rise time measured from –100 mV to +100 mV 0.35 ns tCLKRISE, Output clock rise time, Rise time measured from –100 mV to +100 mV 0.35 ns tCLKFALL output clock fall time PARALLEL CMOS MODE tSU Data setup time Data valid to zero crossing of CLKOUT 1.5 ns tH Data hold time Zero crossing of CLKOUT to data becoming invalid 3.5 ns tFALL, tRISE Data fall time, data rise time Rise time measured from 30% to 70% of IOVDD 2.5 ns tCLKRISE, Output clock rise time, Rise time measured from 30% to 70% of IOVDD 2.2 ns tCLKFALL output clock fall time 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: OPT8241 |
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