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ST72F324LJ6T5 データシート(PDF) 65 Page - STMicroelectronics |
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ST72F324LJ6T5 データシート(HTML) 65 Page - STMicroelectronics |
65 / 151 page ST72F324L, ST72324BL 65/151 16-BIT TIMER (Cont’d) 10.3.4 Low Power Modes 10.3.5 Interrupts Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). * In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no in- terrupt event for these flags. 10.3.6 Summary of Timer modes 1) See note 4 in Section 10.3.3.5 One Pulse Mode 2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode 3) See note 4 in Section 10.3.3.6 Pulse Width Modulation Mode 4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be generated, OCF2 is forced by hardware to 0. 5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0. Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 * Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 * Yes No Timer Overflow event TOF TOIE Yes No MODES TIMER RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes2)5) Yes Yes4) Output Compare (1 and/or 2) Yes Yes5) Yes Yes4) One Pulse Mode No Not Recommended1)5) No Partially 2) PWM Mode No Not Recommended3)5) No No 1 |
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同様の説明 - ST72F324LJ6T5 |
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