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AD73311L データシート(PDF) 10 Page - Analog Devices |
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AD73311L データシート(HTML) 10 Page - Analog Devices |
10 / 37 page REV. A AD73311L –9– FUNCTIONAL DESCRIPTION Encoder Channel The encoder channel consists of an input configuration block, a switched capacitor PGA and a sigma-delta analog-to-digital converter (ADC). An on-board digital filter, which forms part of the sigma-delta ADC, also performs critical system-level filtering. Due to the high level of oversampling, the input anti- alias requirements are reduced such that a simple single pole RC stage is sufficient to give adequate attenuation in the band of interest. Input Configuration Block The input configuration block consists of a multiplexing arrange- ment that allows selection of various input configurations. This includes ADC input selection from either the VINP, VINN pins or from the DAC output via the Analog Loop-Back (ALB) arrangement. Differential inputs can be inverted and it is also possible to use the device in single-ended mode, which allows the option of using the VINP, VINN pins as two separate single-ended inputs, either of which can be selected under software control. Programmable Gain Amplifier The encoder section’s analog front end comprises a switched capacitor PGA that also forms part of the sigma-delta modulator. The SC sampling frequency is DMCLK/8. The PGA, whose programmable gain settings are shown in Table III, may be used to increase the signal level applied to the ADC from low output sources such as microphones, and can be used to avoid placing external amplifiers in the circuit. The input signal level to the sigma-delta modulator should not exceed the maximum input voltage permitted. The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2) in Control Register D. Table III. PGA Settings for the Encoder Channel IGS2 IGS1 IGS0 Gain (dB) 00 0 0 00 1 6 01 0 12 01 1 18 10 0 20 10 1 26 11 0 32 11 1 38 ADC The ADC consists of an analog sigma-delta modulator and a digital antialiasing decimation filter. The sigma-delta modu- lator noise-shapes the signal and produces 1-bit samples at a DMCLK/8 rate. This bitstream, representing the analog input signal, is input to the antialiasing decimation filter. The decima- tion filter reduces the sample rate and increases the resolution. Analog Sigma-Delta Modulator The AD73311L input channel employs a sigma-delta conver- sion technique, which provides a high resolution 16-bit output with system filtering being implemented on-chip. Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73311L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth, up to FS/2 = DMCLK/16 (Figure 6a). This means that the noise in the band of interest is much reduced. Another complementary feature of sigma-delta converters is the use of a technique called noise-shaping. This technique has the effect of pushing the noise from the band of interest to an out-of-band position (Figure 6b). The combi- nation of these techniques, followed by the application of a digital filter, reduces the noise in band sufficiently to ensure good dynamic performance from the part (Figure 6c). BAND OF INTEREST FS/2 DMCLK/16 a. BAND OF INTEREST NOISE-SHAPING FS/2 DMCLK/16 b. BAND OF INTEREST FS/2 DMCLK/16 DIGITAL FILTER c. Figure 6. Sigma-Delta Noise Reduction Figure 7 shows the various stages of filtering that are employed in a typical AD73311L application. In Figure 7a we see the transfer function of the external analog antialias filter. Even though it is a single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency. This also shows the major difference between the initial oversampling rate and the bandwidth of interest. In Figure 7b, the signal and noise-shaping responses of the sigma-delta modulator are shown. The signal response provides further rejection of any high frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail of Figure 7c shows the response of the digital decimation filter (Sinc-cubed response) with nulls every multiple of DMCLK/256, which is the decimation filter update rate. The final detail in Figure 7d shows the application of a final antialias filter in the DSP engine. This has the advantage of being implemented according to the user’s requirements and available MIPS. The filtering in Figures 7a through 7c is imple- mented in the AD73311L. |
同様の部品番号 - AD73311L |
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同様の説明 - AD73311L |
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