AD7843

Rev. B | Page 6 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

10

8

9

11

12

13

14

15

16

AD7843

TOP VIEW

(Not to Scale)

X+

Y+

X–

Y–

GND

IN3

IN4

DCLK

CS

DIN

BUSY

DOUT

PENIRQ

Figure 3. Pin Configuration QSOP/TSSOP

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 10

directly together.

2

X+

X+ Position Input. ADC Input Channel 1.

3

Y+

Y+ Position Input. ADC Input Channel 2.

4

X−

X− Position Input.

5

Y−

Y− Position Input.

6

GND

Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and any external

reference signal should be referred to this GND voltage.

7

IN3

Auxiliary Input 1. ADC Input Channel 3.

8

IN4

Auxiliary Input 2. ADC Input Channel 4.

9

Reference Input for the AD7843. An external reference must be applied to this input. The voltage range for the

11

PENIRQ

Pen Interrupt. CMOS logic open-drain output (requires 10 kΩ to 100 kΩ pull-up register externally).

12

DOUT

Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a serial data stream.

The bits are clocked out on the falling edge of the DCLK input. This output is high impedance when CS is high.

13

BUSY

BUSY Output. Logic Output. This output is high impedance when CS is high.

14

DIN

Data In. Logic input. Data to be written to the AD7843 control register is provided on this input and is clocked into

the register on the rising edge of DCLK (see the Control Register section).

15

CS

Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating conversions on the

AD7843 and also enables the serial input/output register.

16

DCLK

External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part. This clock input

is also used as the clock source for the AD7843 conversion process.