ADE9000ACPZ datasheet(34/73 Pages) AD

部品番号	ADE9000ACPZ

部品情報	High Performance, Multiphase Energy Power Quality Monitoring IC

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Data Sheet

ADE9000

Rev. A | Page 33 of 72

The SELFREQ bit in the ACCMODE register selects whether

the network is 50 Hz or 60 Hz. Then, the UPERIOD_SEL bit in

the CONFIG2 register selects whether to use a measured line

period or a user configured value in the USER_PERIOD

register to set the number of samples used in the calculation.

An offset correction register is available for improved

performance with small input signal levels, xRMS1012OS. The

xRMS1012 register reading with full-scale inputs is 52,702,092d.

The signal chain is shown in Figure 70.

Dip and Swell Indication

The ADE9000 monitors rms½ value on voltage channels to

determine a dip and swell event. If the voltage goes below a

threshold specified in the DIP_LVL register for a user configured

number of half cycles in the DIP_CYC register, the corresponding

DIPA, DIPB, and DIPC bits are set in the STATUS1 register.

The minimum rms½ value measured during the dip is stored in

the corresponding DIPA, DIPB, and DIPC registers.

Similarly, if the voltage goes above a threshold specified in the

SWELL_LVL register for a user configured number of half

cycles in the SWELL_CYC register, the corresponding SWELLA,

SWELLB, and SWELLC bits are set in the STATUS1 register.

The maximum rms½ value measured during the dip is stored in

the corresponding SWELLA, SWELLB, and SWELLC registers.

The dip and swell event generates an interrupt on the IRQ1 pin and

also generates an event on the CF4/EVENT/DREADY pin.

Overcurrent Indication

The ADE9000 monitors the rms½ value on current channels to

determine overcurrent events. If a rms½ current is greater than

the user configured threshold in the OILVL register, the OI bit

in the STATUS1 register is set. The overcurrent event generates

an interrupt on the IRQ1 pin.

The OC_EN bits in the CONFIG3 register select which phases

to monitor for overcurrent events. The OIPHASE bits in the

OISTATUS register indicate which current channels exceeded

the threshold. The overcurrent value is stored in the

corresponding OIA, OIB, or OIC registers.

Peak Detection

The ADE9000 records the peak value measured on the current

and voltage channels from the xI_PCF and xV_PCF waveforms.

The PEAKSEL bits in the CONFIG3 register allow the user to

select which phases to monitor.

The IPEAK register stores the peak current value in the

IPEAKVAL bits and indicates which phase currents reached the

value in the IPPHASE bits. IPEAKVAL is equal to xI_PCF/25.

Similarly, VPEAK stores the peak voltage value in the VPEAKVAL

bits. VPEAKVAL is equal to xV_PCF/25. After a read, the VPEAK

and IPEAK registers reset.

Power Factor

The power factor calculation, one for each channel (APF, BPF,

and CPF), is updated every 1.024 sec.

The sign of the APF calculation follows the sign of AWATT. To

determine if power factor is leading or lagging, refer to the sign

of the total or fundamental reactive energy and the sign of the

xPF or xWATT value, as indicated in Figure 71.

CAPACITIVE:

CURRENT LEADS

VOLTAGE

INDUCTIVE:

CURRENT LAGS

VOLTAGE

WATT

90° LAGGING

INDUCTIVE:

CURRENT LAGS

VOLTAGE

CAPACITIVE:

CURRENT LEADS

VOLTAGE

WATT (–)

VAR (+)

QUADRANT II

WATT (+)

VAR (+)

QUADRANT I

WATT (–)

VAR (–)

QUADRANT III

WATT (+)

VAR (–)

QUADRANT IV

WATT(+) INDICATES POWER RECEIVED (IMPORTED FROM GRID)

WATT(–) INDICATES POWER DELIVERED (EXPORTED TO GRID)

θ2 = 60°

θ1 = –30°

POWER FACTOR 1

= 0.866 CAP

POWER FACTOR 2

= 0.5 IND

Figure 71. Active Power and VAR Sign for Capacitive and Inductive Loads

The power factor result is stored in 5.27 format. The highest

power factor value is 0x07FF FFFF, which corresponds to a power

factor of 1. A power factor of −1 is stored as 0xF800 0000. To

determine the power factor from the xPF register value, use the

following equation:

Power Factor = xPF × 2−27

Total Harmonic Distortion (THD)

A THD calculation is available on the IA, IB, IC, VA, VB, and

VC channels in the AITHD, BITHD, CITHD, AVTHD,

BVTHD, and CVTHD registers, respectively. THD updates

once every second.

The THD calculation is stored in signed 5.27 format. The

highest THD value is 0x2000 0000, which corresponds to a

THD of 400%. To calculate the THD value as a percentage, use

the following equation:

%THD on Current Channel A = AITHD × 2−27 × 100%

Resampling 128 Points per Cycle

The ADE9000 resamples the input data to provide 128 points

per line cycle, independent of the input line frequency. The

resampled data is available for all current channels and voltage

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