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AD6677BCPZRL7 データシート(PDF) 2 Page - Analog Devices |
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AD6677BCPZRL7 データシート(HTML) 2 Page - Analog Devices |
2 / 48 page AD6677 Data Sheet Rev. C | Page 2 of 48 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 ADC DC Specifications............................................................... 4 ADC AC Specifications ............................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Equivalent Circuits......................................................................... 16 Theory of Operation ...................................................................... 17 ADC Architecture ...................................................................... 17 Analog Input Considerations.................................................... 17 Voltage Reference ....................................................................... 19 Clock Input Considerations...................................................... 19 Power Dissipation and Standby Mode..................................... 22 Noise Shaping Requantizer ........................................................... 23 22% Bandwidth Mode (>40 MHz at 184.32 MSPS) .............. 23 33% Bandwidth Mode (>60 MHz at 184.32 MSPS) .............. 24 Digital Outputs ............................................................................... 25 JESD204B Transmit Top Level Description............................ 25 ADC Overrange and Gain Control.......................................... 30 DC Correction (DCC)................................................................... 32 DC Correction Bandwidth........................................................ 32 DC Correction Readback.......................................................... 32 DC Correction Freeze................................................................ 32 DC Correction Enable Bits ....................................................... 32 Serial Port Interface (SPI).............................................................. 33 Configuration Using the SPI..................................................... 33 Hardware Interface..................................................................... 33 SPI Accessible Features.............................................................. 33 Memory Map .................................................................................. 35 Reading the Memory Map Register Table............................... 35 Memory Map Register Table..................................................... 36 Memory Map Register Descriptions........................................ 40 Applications Information .............................................................. 44 Design Guidelines ...................................................................... 44 Outline Dimensions....................................................................... 45 Ordering Guide .......................................................................... 45 REVISION HISTORY 1/16—Rev. B to Rev. C Changes to General Description Section ...................................... 3 Changes to Nyquist Clock Input Section .................................... 19 Changes to JESD204B Overview Section.................................... 25 Changes to Figure 52...................................................................... 28 Change to Table 17 ......................................................................... 38 5/14—Rev. A to Rev. B Change to RF Clock Rate Parameter, Table 3 ............................... 6 Change to Pin 11, Table 8 .............................................................. 11 Change to RF Clock Input Options Section................................ 20 Changes to Transfer Register Map Section ................................. 35 Changes to Table 17........................................................................ 37 Change to JESD204B Link Control 2 (Address 0x60)............... 41 3/14—Rev. 0 to Rev. A Changes to Data Output Parameters, Table 4................................8 Changes to Figure 3...........................................................................9 4/13—Revision 0: Initial Version |
同様の部品番号 - AD6677BCPZRL7 |
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同様の説明 - AD6677BCPZRL7 |
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