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SN74F657NT データシート(PDF) 1 Page - Texas Instruments

部品番号 SN74F657NT
部品情報  OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

SN74F657NT データシート(HTML) 1 Page - Texas Instruments

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T/R
A1
A2
A3
A4
A5
VCC
A6
A7
A8
ODD/EVEN
ERR
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
DW OR NT PACKAGE
(TOP VIEW)
SN74F657
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER
AND 3-STATE OUTPUTS
SDFS027A – D3217, JANUARY 1989 – REVISED OCTOBER 1993
Copyright
© 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Combines ′F245 and ′F280B Functions in
One Package
High-Impedance N-P-N Inputs for Reduced
Loading (70
µA in Low and High States)
High Output Drive and Light Bus Loading
3-State B Outputs Sink 64 mA and Source
15 mA
Input Diodes for Termination Effects
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The SN74F657 contains eight noninverting
buffers with 3-state outputs and an 8-bit parity
generator/checker. It is intended for bus-oriented
applications. The buffers have a specified current
sinking capability of 24 mA at the A port and 64 mA
at the B port.
The transmit/receive (T/R) input determines the direction of the data flow through the bidirectional transceivers.
When T/R is high, data is transmitted from the A port to the B port. When T/R is low, data is received at the A port
from the B port.
When the output enable (OE) input is high, both the A and B ports are placed in a high-impedance state
(disabled). The ODD/EVEN input allows the user to select between odd or even parity systems. When
transmitting from A port to B port (T/R high), PARITY is an output from the generator/checker. When receiving
from B port to A port (T/R low), PARITY is an input.
When transmitting (T/R high), the parity select (ODD/EVEN) input is made high or low as appropriate. The A port
is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by
ODD/EVEN and the number of high bits on A port. When ODD/EVEN is low (for even parity) and the number
of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port
is even, the PARITY will be low, keeping even parity.
When in the receive mode (T/R low), the B port is polled to determine the number of high bits. If ODD/EVEN
is low (for even parity) and the number of highs on B port is:
1.
Odd and the PARITY input is high, then ERR will be high signifying no error.
2.
Even and the PARITY input is high, then ERR will be low indicating an error.
The SN74F657 is characterized for operation from 0
°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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