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MT9P031 データシート(PDF) 21 Page - ON Semiconductor |
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MT9P031 データシート(HTML) 21 Page - ON Semiconductor |
21 / 32 page MT9P031 www.onsemi.com 21 Figure 24. GRR Snapshot Timing TRIGGER STROBE FV LV DOUT TRIGGER STROBE FV LV DOUT (a) GRR Snapshot (b) GRR Bulb TSE TSW TT2 TSW TSE TT2 VB x tROW + 2000 xtACLK tROW 8 x t ROW tROW 8 x tROW First Row Exposure First Row Exposure VB xtROW + 2000 xtACLK Second Row Exposure Second Row Exposure SW x tROW + 2000 x tACLK SW x tROW + 2000 xtACLK TT1 TT1 Strobe Control To support synchronization of the exposure with external events such as a flash or mechanical shutter, the MT9P031 produces a STROBE output. By default, this signal is asserted for approximately the time that all rows are simultaneously exposing, minus the vertical blanking time, as shown in Figure 23 and Figure 24. Also indicated in these figures are the leading and trailing edges of STROBE, which an be configured to occur at one of several timepoints. The leading edge of STROBE occurs at STROBE_Start, and the trailing edge at STROBE_End, which are set to codes described in Table 14. Table 14. STROBE TIMEPOINTS Symbol Timepoint Code TT1 Trigger 1 (start of shutter scan) – TSE Start of exposure (all rows simultaneously exposing) offset by VB 1 TSW End of shutter width (expiration of the internal shutter width counter) 2 TT2 Trigger 2 (start of readout scan) 3 If STROBE_Start and STROBE_End are set to the same timepoint, the strobe is a tROW wide pulse starting at the STROBE_Start timepoint. If the settings are such that the strobe would occur after the trailing edge of FV, the strobe may be only tACLK wide; however, because there is no concept of a row at that time. The sense of the STROBE signal can be inverted by setting Invert_Strobe (R0x1E[5] = 1. To use strobe as a flash in snapshot modes or with mechanical shutter, set the Strobe_Enable register bit field R0x1E[4] = 1. Signal Chain and Datapath The signal chain and datapath are shown in Figure 25. Each color is processed independently, including separate gain and offset settings. Voltages sampled from the pixel array are first passed through an analog gain stage, which can produce gain factors between 1 and 8. An analog offset is then applied, and the signal is sent through a 12-bit analog-to-digital converter. In the digital space, a digital gain factor of between 1 and 16 is applied, and then a digital |
同様の部品番号 - MT9P031_17 |
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同様の説明 - MT9P031_17 |
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