データシートサーチシステム |
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PYTHON480 データシート(PDF) 46 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 46 Page - ON Semiconductor |
46 / 69 page PYTHON 480 www.onsemi.com 46 REGISTER MAP Table 33. REGISTER MAP Address Offset Address Bit Field Register Name Default (Hex) Default Description Type Chip ID [Block Offset: 0] 0 0 chip_id 0x5004 20484 Chip ID Status [15:0] id 0x5004 20484 Chip ID 1 1 reserved 0x0000 0 Reserved Status [3:0] reserved 0x0 0 Reserved [9:8] Resolution 0x0 0 Chip Resolution [11:10] reserved 0x0 0 Reserved 2 2 chip_configuration 0x0000 0 Chip General Configuration RW [0] color 0x0 0 Color/Monochrome Configuration ‘0’: Monochrome ‘1’: Color [1] reserved 0x0 0 Reserved [15:2] reserved 0x0 0 Reserved Reset Generator [Block Offset: 8] 0 8 soft_reset_pll 0x0099 153 PLL Soft Reset Configuration RW [3:0] pll_soft_reset 0x9 9 PLL Reset 0x9: Soft Reset State others: Operational [7:4] pll_lock_soft_reset 0x9 9 PLL Lock Detect Reset 0x9: Soft Reset State others: Operational 1 9 soft_reset_cgen 0x0009 9 Clock Generator Soft Reset RW [3:0] cgen_soft_reset 0x9 9 Clock Generator Reset 0x9: Soft Reset State others: Operational 2 10 soft_reset_analog 0x0999 2457 Analog Block Soft Reset RW [3:0] mux_soft_reset 0x9 9 Column MUX Reset 0x9: Soft Reset State others: Operational [7:4] afe_soft_reset 0x9 9 AFE Reset 0x9: Soft Reset State others: Operational [11:8] ser_soft_reset 0x9 9 Serializer Reset 0x9: Soft Reset State others: Operational PLL [Block Offset: 16] 0 16 power_down 0x0004 4 PLL Configuration RW [0] pwd_n 0x0 0 PLL Power Down ’0’: Power Down, ’1’: Operational [1] enable 0x0 0 PLL Enable ’0’: disabled, ’1’: enabled [2] bypass 0x1 1 PLL Bypass ’0’: PLL Active, ’1’: PLL Bypassed 1 17 reserved 0x2113 8467 Reserved RW [7:0] reserved 0x13 19 Reserved [12:8] reserved 0x1 1 Reserved [14:13] reserved 0x1 1 Reserved |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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