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PYTHON480 データシート(PDF) 47 Page - ON Semiconductor

部品番号 PYTHON480
部品情報  Megapixel Global Shutter CMOS Image Sensor
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
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PYTHON 480
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47
Table 33. REGISTER MAP (continued)
Address
Offset
Type
Description
Default
Default
(Hex)
Register Name
Bit Field
Address
I/O [Block Offset: 20]
0
20
config1
0x0000
0
IO Configuration
RW
[0]
clock_in_pwd_n
0x0
0
Power down Clock Input
[9:8]
reserved
0x0
0
Reserved
[10]
reserved
0x0
0
Reserved
PLL Lock Detector [Block Offset: 24]
0
24
pll_lock
0x0000
0
PLL Lock Indication
Status
[0]
lock
0x0
0
PLL Lock Indication
2
26
reserved
0x2280
8832
Reserved
RW
[7:0]
reserved
0x80
128
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
3
27
reserved
0x3D2D
15661
Reserved
RW
[7:0]
reserved
0x2D
45
Reserved
[15:8]
reserved
0x3D
61
Reserved
Clock Generator [Block Offset: 32]
0
32
config0
0x2014
8212
Clock Generator Configuration
RW
[0]
enable_analog
0x0
0
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode of CGEN block
‘0’: divide by 5 mode (10-bit mode)
[4]
enable_clkgate
0x1
1
Clock gate on master distribution
‘0’: Clock active
‘1’: Clock inactive (gated)
[11:8]
reserved
0x0
0
Reserved
[14:12]
reserved
0x2
2
Reserved
General Logic [Block Offset: 34]
0
34
config0
0x0000
0
Clock Generator Configuration
RW
[0]
enable
0x0
0
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
0
38
reserved
0x0000
0
Reserved
RW
[15:0]
reserved
0x0000
0
Reserved
Image Core [Block Offset: 40]
0
40
image_core_config0
0x0000
0
Image Core Configuration
RW
[0]
imc_pwd_n
0x0
0
Image Core Power Down
‘0’: powered down,
‘1’: powered up
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
1
41
image_core_config1
0x085A
2138
Image Core Configuration
RW


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