データシートサーチシステム |
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PYTHON480 データシート(PDF) 12 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 12 Page - ON Semiconductor |
12 / 69 page PYTHON 480 www.onsemi.com 12 OVERVIEW Figure 11 gives an overview of the major functional blocks of the sensor. Figure 11. Block Diagram Pixel Array Data Formatting Serializers & LVDS Interface LVDS Clock Input LVDS Interface (Data, Sync, Clock) 2 analog channels 2 x 10 bit digital channels 1 x 10 bit digital channels Column Structure Image Core Bias Image Core Automatic Exposure Control (AEC) Clock Distribution CMOS Clock Input LVDS Receiver PLL Control & Registers CMOS Interface CMOS Interface (Data, frame_valid, line_valid) Analog Front End (AFE) Image Core The image core consists of: • Pixel Array • Address Decoders and Row Drivers • Pixel Biasing The PYTHON 480 pixel array contains 808 (H) x 608 (V) readout pixels with a pixel pitch of 4.8 mm, inclusive of 8 pixel rows and 8 pixel columns at every side to allow for reprocessing or color reconstruction. The sensors use in−pixel CDS architecture, which makes it possible to achieve a low noise read out of the pixel array in global shutter mode with CDS. The function of the row drivers is to access the image array line by line, or all lines together, to reset or read the pixel data. The row drivers are controlled by the on−chip sequencer and can access the pixel array. The pixel biasing block guarantees that the data on a pixel is transferred properly to the column multiplexer when the row drivers select a pixel line for readout. Phase Locked Loop The PLL accepts a (low speed) clock and generates the required high speed clock. Input clock frequency is 68 MHz. |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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