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PYTHON480 データシート(PDF) 13 Page - ON Semiconductor

部品番号 PYTHON480
部品情報  Megapixel Global Shutter CMOS Image Sensor
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メーカー  ONSEMI [ON Semiconductor]
ホームページ  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

PYTHON480 データシート(HTML) 13 Page - ON Semiconductor

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PYTHON 480
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LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Input clock frequency is 340 MHz. The clock input needs
to be terminated with a 100
W resistor.
Column Multiplexer
All pixels of one image row are stored in the column
sample−and−hold (S/H) stages. These stages store both the
reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 2 parallel differential outputs operating at a
frequency of 34 MHz. At this stage, the reset signal and
integrated signal values are transferred into an
FPN−corrected differential signal. A programmable gain of
1x, 2x, or 3.5x can be applied to the signal. The column
multiplexer
also
supports
read−1−skip−1
and
read−2−skip−2 mode. Enabling this mode increases the
frame rate, with a decrease in resolution but same field of
view.
Bias Generator
The bias generator generates all required reference
voltages and bias currents used on chip. An external resistor
of 47 k
W, connected between pin IBIAS_MASTER and
gnd_33, is required for the bias generator to operate
properly.
Analog Front End
The AFE contains 2 channels, each containing a PGA and
a 10−bit ADC.
For each of the 2 channels, a pipelined 10−bit ADC is used
to convert the analog image data into a digital signal, which
is delivered to the data formatting block. A black calibration
loop is implemented to ensure that the black level is mapped
to match the correct ADC input level.
Data Formatting
The data block receives data from two ADCs and
multiplexes this data to one data stream. A cyclic
redundancy check (CRC) code is calculated on the passing
data.
A frame synchronization data block transmits
synchronization codes such as frame start, line start, frame
end, and line end indications.
The data block calculates a CRC once per line for every
channel. This CRC code can be used for error detection at the
receiving end.
Serializer and LVDS Interface (LVDS Mode only)
The serializer and LVDS interface block receives the
formatted data from the data formatting block. This data is
serialized and transmitted by the LVDS 340 MHz output
driver.
The maximum output data rate is 680 Mbps per channel.
In addition to the LVDS data outputs, two extra LVDS
outputs are available. One of these outputs carries the output
clock, which is skew aligned to the output data channels. The
second LVDS output contains frame format synchronization
codes to serve system−level image reconstruction.
CMOS Interface
Frame synchronization information is communicated by
means of frame and line valid strobes. Both CMOS and
LVDS outputs are active at the same time. LVDS channels
can be powered down through SPI control when using the
CMOS outputs.
Sequencer
The sequencer:
Controls the image core. Starts and stops integration
and control pixel readout.
Operates the sensor in master or slave mode.
Applies the window settings. Organizes readouts so that
only the configured windows are read.
Controls the column multiplexer and analog core.
Applies gain settings and subsampling modes at the
correct time, without corrupting image data.
Starts up the sensor correctly when leaving standby
mode.
Automatic Exposure Control
The AEC block implements a control system to modulate
the exposure of an image. Both integration time and gains
are controlled by this block to target a predefined
illumination level.


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