データシートサーチシステム |
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PYTHON480 データシート(PDF) 18 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 18 Page - ON Semiconductor |
18 / 69 page PYTHON 480 www.onsemi.com 18 Check the PLL_lock flag 24[0] by reading the SPI register. When the flag is set, the ‘Enable Clock Management− Part 2’ action can be continued. When PLL is not used, this step can be bypassed as shown in Figure 16 on page 16. Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1 Upload # Address Data Description LVDS Mode with PLL 1 2 0x0000 Monochrome sensor 0x0001 Color sensor 2 8 0x0000 Release PLL soft reset 3 16 0x0003 Enable PLL 4 17 0x2113 Configure PLL 5 20 0x0000 Configure clock management 6 26 0x2280 Configure PLL lock detector 7 27 0x3D2D Configure PLL lock detector 8 32 0x7014 Configure clock management Enable Clock Management − Part 2 The next step to configure the clock management consists of SPI uploads which enables all internal clock distribution. The required uploads are listed in Table 4. Note that it is important to follow the upload sequence listed in Table 7. Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2 Upload # Address Data Description LVDS Mode with PLL 1 9 0x0000 Release clock generator soft reset 2 32 0x7007 Enable logic clock 3 34 0x0001 Enable logic blocks Required Register Upload In this phase, the ‘reserved’ register settings are uploaded through the SPI register. Different settings are not allowed and may cause the sensor to malfunction. The required uploads can be downloaded from the MyON website. |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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