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PYTHON480 データシート(PDF) 21 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 21 Page - ON Semiconductor |
21 / 69 page PYTHON 480 www.onsemi.com 21 Disable Clock Management − Part 2 The ‘Disable Clock Management’ action stops the internal clocking to further decrease the power dissipation. This action can be implemented with the SPI uploads as shown in Table 13. Table 12. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 2 Upload # Address Data Description LVDS Mode with PLL 1 34 0x0000 Soft reset clock generator 2 32 0x7004 Disable logic clock 3 9 0x0000 Disable logic blocks Disable Clock Management − Part 1 The ‘Disable Clock Management’ action stops the internal clocking to further decrease the power dissipation. This action can be implemented with the SPI uploads as shown in Table 13. Table 13. DISABLE CLOCK MANAGEMENT REGISTER UPLOAD: PART 1 Upload # Address Data Description LVDS Mode with PLL 1 16 0x0099 Soft reset PLL 2 8 0x0000 Disable PLL Power Down Sequence Figure 18 illustrates the timing diagram of the preferred power down sequence. It is important that the sensor is in reset before the clock input stops running. Otherwise, the internal PLL becomes unstable and the sensor gets into an unknown state. This can cause high peak currents. The same applies for the ramp down of the power supplies. The preferred order to ramp down the supplies is first vdd_pix, second vdd_33, and finally vdd_18. Any other sequence can cause high peak currents. NOTE: The ‘clock input’ can be the LVDS clock input (lvds_clock_inn/p) in case the PLL is bypassed. Figure 18. Power Down Sequence reset_n vdd_18 vdd_33 clock input vdd_pix > 10us > 10us > 10us > 10us |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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