データシートサーチシステム |
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PYTHON480 データシート(PDF) 26 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 26 Page - ON Semiconductor |
26 / 69 page PYTHON 480 www.onsemi.com 26 Serial Peripheral Interface The sensor configuration registers are accessed through an SPI. The SPI consists of four wires: • sck: Serial Clock • ss_n: Active Low Slave Select • mosi: Master Out, Slave In, or Serial Data In • miso: Master In, Slave Out, or Serial Data Out The SPI is synchronous to the clock provided by the master (sck) and asynchronous to the sensor’s system clock. When the master wants to write or read a sensor’s register, it selects the chip by pulling down the Slave Select line (ss_n). When selected, data is sent serially and synchronous to the SPI clock (sck). Figure 21 shows the communication protocol for read and write accesses of the SPI registers. The PYTHON 480 image sensors use 9−bit addresses and 16−bit data words. Data driven by the system is colored blue in Figure 21, while data driven by the sensor is colored yellow. The data in grey indicates high−Z periods on the miso interface. Red markers indicate sampling points for the sensor (mosi sampling); green markers indicate sampling points for the system (miso sampling during read operations). The access sequence is: 3. Select the sensor for read or write by pulling down the ss_n line. 4. One SPI clock cycle after selecting the sensor, the 9−bit data is transferred, most significant bit first. The sck clock is passed through to the sensor as indicated in Figure 21. The sensor samples this data on a rising edge of the sck clock (mosi needs to be driven by the system on the falling edge of the sck clock). 5. The tenth bit sent by the master indicates the type of transfer: high for a write command, low for a read command. 6. Data transmission: - For write commands, the master continues sending the 16−bit data, most significant bit first. - For read commands, the sensor returns the requested address on the miso pin, most significant bit first. The miso pin must be sampled by the system on the falling edge of sck (assuming nominal system clock frequency and maximum 10 MHz SPI frequency). 7. When data transmission is complete, the system deselects the sensor one clock period after the last bit transmission by pulling ss_n high. Note that the maximum frequency for the SPI interface scales with the input clock frequency, bit depth and LVDS output multiplexing as described in Table 5. Consecutive SPI commands can be issued by leaving at least two SPI clock periods between two register uploads. Deselect the chip between the SPI uploads by pulling the ss_n pin high. Figure 21. SPI Read and Write Timing Diagram .. A1 A0 `1' A8 D15 D14 .. .. .. .. D1 D0 sck mosi ss_n miso A7 .. .. .. A1 A0 `0' A8 sck mosi ss_n miso A7 .. .. D15 D14 .. .. .. .. D1 D0 ts_mosi th_mosi t_sssck t_sckss ts _miso th_miso t_sckss t_sssck ts _mos i th_mosi tsck tsck SPI − WRITE SPI − READ |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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