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PYTHON480 データシート(PDF) 4 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 4 Page - ON Semiconductor |
4 / 69 page PYTHON 480 www.onsemi.com 4 Table 5. ELECTRICAL SPECIFICATIONS Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8) Parameter Description Min Typ Max Unit Power Supply Parameters − LVDS (NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.) vdd_33 Supply voltage, 3.3 V 3.2 3.3 3.4 V Idd_33 Current consumption 3.3 V supply 48 mA vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V Idd_18 Current consumption 1.8 V supply 59 mA vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V Idd_pix Current consumption pixel supply 0.04 mA Ptot Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V 265 mW Pstby_lp Power consumption in low power standby mode < 1 mW Popt Power consumption at lower pixel rates Configurable Power Supply Parameters − CMOS vdd_33 Supply voltage, 3.3 V 3.2 3.3 3.4 V Idd_33 Current consumption 3.3 V supply 33 mA vdd_18 Supply voltage, 1.8 V 1.7 1.8 1.9 V Idd_18 Current consumption 1.8 V supply 37 mA vdd_pix Supply voltage, pixel 3.25 3.3 3.35 V Idd_pix Current consumption pixel supply 3 mA Ptot Total power consumption 185 mW Pstby_lp Power consumption in low power standby mode < 0.5 mW Popt Power consumption at lower pixel rates Configurable I/O − LVDS (EIA/TIA−644): Conforming to standard/additional specifications and deviations listed fserdata Data rate on data channels DDR signaling − 1 data channel, 1 synchronization channel 680 Mbps fserclock Clock rate of output clock Clock output for mesochronous signaling 340 MHz Vicm LVDS input common mode level 0.3 1.25 1.8 V Tccsk Channel to channel skew (Training pattern allows per channel skew correction) 50 ps I/O − CMOS 1.8 V Signal levels (Note 9) fpardata Data rate on parallel channels (10−bit) 68 Mbps ViL CMOS input low level −0.2 0.8 V ViH CMOS input high level 1.2 3.6 V Electrical Interface − LVDS fin Input clock rate when PLL used 68 MHz Input clock rate when PLL used 340 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. All parameters are characterized for DC conditions after thermal equilibrium is established. 6. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 7. Minimum and maximum limits are guaranteed through test and design. 8. Refer to ACSPYTHON480 available at the Image Sensor Portal for detailed acceptance criteria specifications. 9. CMOS inputs are compatible with 3.3 V signal levels. 10.Longer integration times are possible, but with possible image quality trade−offs. 11. Data is clocked on the rising edge of the output clock. This can be changed to the falling edge by register 130[8] |
同様の部品番号 - PYTHON480 |
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同様の説明 - PYTHON480 |
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