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PYTHON480 データシート(PDF) 41 Page - ON Semiconductor |
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PYTHON480 データシート(HTML) 41 Page - ON Semiconductor |
41 / 69 page PYTHON 480 www.onsemi.com 41 • Window Identification Frame synchronization codes are always followed by a 3−bit window identification (bits 2:0). This is an integer number, ranging from 0 to 7, indicating the active window. If more than one window is active for the current cycle, the highest window ID is transmitted. • Data Classification Codes For the remaining cycles, the sync channel indicates the type of data sent through the data links: black pixel data (BL), image data (IMG), or training pattern (TR). These codes are programmable by a register setting. The default values are listed in Table 30. Table 30. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES Sync Word Bit Position Register Address Default Value Description 9:0 118 [9:0] 0x015 Black pixel data (BL). This data is not part of the image. The black pixel data is used internally to correct channel offsets. 9:0 119 [9:0] 0x035 Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the image). 9:0 125 [9:0] 0x059 CRC value. The data on the data output channels is the CRC code of the finished image data line. 9:0 126 [9:0] 0x3A6 Training pattern (TR). The sync channel sends out the training pattern which can be programmed by a register setting. Training Patterns on Data Channels During idle periods, the data channels transmit training patterns, indicated on the sync channel by a TR code. These training patterns are configurable independent of the training code on the sync channel as shown in Table 31. Table 31. TRAINING CODE ON SYNC CHANNEL IN Sync Word Bit Position Register Address Default Value Description [9:0] 116 [9:0] 0x3A6 Data channel training pattern. The data output channels send out the training pattern, which can be programmed by a register setting. The default value of the training pattern is 0x3A6, which is identical to the training pattern indication code on the sync channel. Cyclic Redundancy Code At the end of each line, a CRC code is calculated to allow error detection at the receiving end. Each data channel transmits a CRC code to protect the data words sent during the previous cycles. Idle and training patterns are not included in the calculation. The sync channel is not protected. A special character (CRC indication) is transmitted whenever the data channels send their respective CRC code. The polynomial is x10 +x9 +x6 +x3 +x2 + x + 1. The CRC encoder is seeded at the start of a new line and updated for every (valid) data word received. The CRC seed is configurable using the crc_seed register. When ‘0’, the CRC is seeded by all−‘0’; when ‘1’ it is seeded with all−‘1’. NOTE: The CRC is calculated for every line. This implies that the CRC code can protect lines from multiple windows. Data Order: LVDS Interface Version To read out the image data through the output channel, the pixel array is organized in kernels. The kernel size is two pixels in x−direction by one pixel in y−direction. Figure 34 indicates how the kernels are organized. The first kernel (kernel [0, 0]) is located in the bottom left corner. The pixel data is transmitted in order. The figures in the following paragraphs represent the data order for a non−mirrored readout (i.e. left−to−right readout). Figure 34. Kernel Organization in Pixel Array (Top View) ROI kernel (403,607) kernel (x_start,y_start) 0 1 pixel array kernel (0,0) |
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同様の説明 - PYTHON480 |
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